Among them, master-slave and pulse-triggered flip-flops are the most efficient in terms of power-delay product. Hence, design and implementation of low power high performance flip-flops with the least possible chip area is the main target of the modern chip manufacturing industry.įlip-flops are broadly classified into three main categories, namely, master-slave, pulse triggered, and differential flip-flops. A design with elevated transistor count occupies a larger area on chip and leads to an increase in the overall manufacturing cost. Clock load is another major concern for digital system designers and several contributions have been reported in the past to reduce clock load and the associated power dissipation in the clocking network. Flip-flops and clock distribution network generally account for 30–70% of the total chip power consumption. The highest operating frequency of clocked digital systems is determined by the flip-flops. However, factors such as high performance, low power, transistor count, clock load, design robustness, power-delay, and power-area tradeoffs are generally considered before choosing a particular flip-flop design. The appropriate selection of flip-flop topologies is instrumental in the design of VLSI integrated circuits such as microprocessors, microcontrollers, and other high complexity chips. Introductionįlip-flops are the key elements used in sequential digital systems. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. Postlayout simulations indicate that mC 2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. The modified C 2MOS based flip-flop designs mC 2MOSff1 and mC 2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC 2MOSff1. Based on the proposed structure, traditional C 2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density.